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final publication# 20405 rev: b amendment/ 0 issue date: february 1996 com?: -7.5/10/12/15/20 ind: -10/12/14/18/24 mach211sp-7/10/12/15/20 high-density ee cmos programmable logic distinctive characteristics n jtag-compatible, 5-v in-system programming n 44 pins n 64 macrocells n 7.5 ns t pd commercial 10 ns t pd industrial n 133 mhz f cnt n 34 bus-friendly inputs and i/os n peripheral component interconnect (pci) compliant (-7/-10) n programmable power-down mode n 32 outputs n 64 flip-?ps; 2 clock choices n 4 ?al26v16 blocks with buried macrocells n improved routing over the mach210 in-system programming in-system programming allows the mach211sp to be programmed while soldered onto a system board. pro- gramming the mach211sp in-system yields numer- ous bene?s at all stages of development: prototyping, manufacturing, and in the ?ld. since insertion into a programmer isn? needed, multiple handling steps and the resulting bent leads are eliminated. the design can be modi?d in-system for design changes and debug- ging while prototyping, programming boards in produc- tion, and ?ld upgrades. the mach211sp offers advantages not available in other cpld architectures with in-system programming. mach devices have extensive routing resources for pin-out retention; design changes resulting in pin-out changes for other cplds cancel the advantages of in-system programming. the mach211sp can be em- ployed in any jtag (ieee 1149.1) compliant chain. general description the mach211sp is a member of amds ee cmos performance plus mach a 2 device family. this device has approximately six times the logic macrocell capa- bility of the popular pal22v10 without loss of speed. the mach211sp consists of four pal a blocks inter- connected by a programmable switch matrix. the four pal blocks are essentially ?al26v16 structures com- plete with product-term arrays and programmable macrocells, which can be programmed as high speed or low power, and buried macrocells. the switch matrix connects the pal blocks to each other and to all input pins, providing a high degree of connectivity between the fully-connected pal blocks. this allows designs to be placed and routed ef?iently. the mach211sp has two kinds of macrocell: output and buried. the mach211sp output macrocell pro- vides registered, latched, or combinatorial outputs with programmable polarity. if a registered con?uration is chosen, the register can be congured as d-type or t-type to help reduce the number of product terms. the register type decision can be made by the designer or by the software. all output macrocells can be con- nected to an i/o cell. if a buried macrocell is desired, the internal feedback path from the macrocell can be used, which frees up the i/o pin for use as an input. the mach211sp has dedicated buried macrocells which, in addition to the capabilities of the output macrocell, also provide input registers or latches for use in synchronizing signals and reducing setup time requirements. the mach211sp is an enhanced version of the mach211, adding the jtag-compatible in-system pro- gramming feature.
2 mach211sp-7/10/12/15/20 block diagram 20405b-1 switch matrix i/o cells macrocells i/o 0 ?/o 7 macrocells 8 8 8 2 clk 0 /i 0 clk 1 /i 1 52 x 68 and logic array and logic allocator 26 2 8 2 oe i/o cells macrocells i/o 8 ?/o 15 macrocells 8 8 8 52 x 68 and logic array and logic allocator 26 8 oe i/o cells macrocells i/o 24 ?/o 31 macrocells 8 8 8 52 x 68 and logic array and logic allocator 26 8 oe i/o cells macrocells i/o 16 ?/o 23 macrocells 8 8 8 52 x 68 and logic array and logic allocator 26 8 oe
mach211sp-7/10/12/15/20 3 connection diagram mach211sp top view 44-pin plcc pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 i/o12 i/o13 i/o14 i/o15 v cc gnd i/o16 i/o17 i/o18 i/o19 i/o20 i/o4 i/o3 i/o2 i/o1 i/o0 gnd v cc i/o31 i/o30 i/o29 i/o28 20405b-2
4 mach211sp-7/10/12/15/20 connection diagram mach211sp top view 44-pin tqfp pin designations clk/i = clock or input gnd = ground i = input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out i/o12 i/o13 i/o14 i/o15 v cc gnd i/o16 i/o17 i/o18 i/o19 i/o20 i/o4 i/o3 i/o2 i/o1 i/o0 gnd v cc i/o31 i/o30 i/o29 i/o28 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 20405b-3
mach211sp-7/10/12/15/20 (coml) 5 ordering information commercial products amd programmable logic products for commercial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations the valid combinations table lists con?urations planned to be supported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combina- tions and to check on newly released combinations. family type mach = macro array cmos high-speed mach 211 sp -7 j c device number 211 = 64 macrocells, 44 pins, power-down mode, bus-friendly inputs and i/os product designation sp = in-system programmable optional processing blank = standard processing operating conditions c = commercial (0 c to +70 c) package type j = 44-pin plastic leaded chip carrier (pl 044) v = 44-pin thin quad flat pack (pqt044) speed -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd valid combinations mach211sp-7 jc, vc mach211sp-10 MACH211SP-12 mach211sp-15 mach211sp-20
6 mach211sp-10/12/14/18/24 (ind) ordering information industrial products amd programmable logic products for industrial applications are available with several ordering options. the order number (valid combination) is formed by a combination of: valid combinations the valid combinations table lists con?urations planned to be supported in volume for this device. consult the local amd sales of?e to con?m availability of speci? valid combina- tions and to check on newly released combinations. device number 211 = 64 macrocells, 44 pins, power-down mode, bus-friendly inputs and i/os product designation sp = in-system programmable family type mach = macro array cmos high-speed mach 211 sp -10 j i optional processing blank = standard processing operating conditions i = industrial (?0 c to +85 c) package type j = 44-pin plastic leaded chip carrier (pl 044) speed -10 = 10 ns t pd -12 = 12 ns t pd -14 = 14.5 ns t pd -18 = 18 ns t pd -24 = 24 ns t pd valid combinations mach211sp-10 ji MACH211SP-12 mach211sp-14 mach211sp-18 mach211sp-24
mach211sp-7/10/12/15/20 7 functional description the mach211sp consists of four pal blocks con- nected by a switch matrix. there are 32 i/o pins feeding the switch matrix. these signals are distributed to the four pal blocks for ef?ient design implementation. there are two clock pins that can also be used as ded- icated inputs. the pal blocks each pal block in the mach211sp (figure 1) contains a 64-product-term logic array, a logic allocator, 8 output macrocells, 8 buried macrocells, and 8 i/o cells. the switch matrix feeds each pal block with 26 inputs. this makes the pal block look effectively like an indepen- dent ?al26v16 with 8 buried macrocells. in addition to the logic product terms, two output enable product terms, an asynchronous reset product term, and an asynchronous preset product term are pro- vided. one of the two output enable product terms can be chosen within each i/o cell in the pal block. all ?p-?ps within the pal block are initialized together. the switch matrix the mach211sp switch matrix is fed by the inputs and feedback signals from the pal blocks. each pal block provides 16 internal feedback signals and 8 i/o feed- back signals. the switch matrix distributes these sig- nals back to the pal blocks in an ef?ient manner that also provides for high performance. the design soft- ware automatically con?ures the switch matrix when ?ting a design into the device. the product-term array the mach211sp product-term array consists of 64 product terms for logic use, and 4 special-purpose product terms. two of the special-purpose product terms provide programmable output enable; one pro- vides asynchronous reset, and one provides asynchro- nous preset. the logic allocator the logic allocator in the mach211sp takes the 64 logic product terms and allocates them to the 16 macrocells as needed. each macrocell can be driven by up to 16 product terms. the design software auto- matically con?ures the logic allocator when ?ting the design into the device. table 1 illustrates which product term clusters are avail- able to each macrocell within a pal block. refer to figure 1 for cluster and macrocell numbers. the macrocell the mach211sp has two types of macrocell: output and buried. the output macrocells can be con?ured as either registered, latched, or combinatorial, with pro- grammable polarity. the macrocell provides internal feedback whether con?ured with or without the ?p-?p. the registers can be con?ured as d-type or t-type, allowing for product-term optimization. the ?p-?ps can individually select one of two clock/ gate pins, which are also available as data inputs. the registers are clocked on the low-to-high transition of the clock signal. the latch holds its data when the gate input is high, and is transparent when the gate input is low. the ?p-?ps can also be asynchronously ini- tialized with the common asynchronous reset and pre- set product terms. the buried macrocells are the same as the output macrocells if they are used for generating logic. in that case, the only thing that distinguishes them from the output macrocells is the fact that there is no i/o cell connection, and the signal is only used internally. the buried macrocell can also be con?ured as an input register or latch. the i/o cell the i/o cell in the mach211sp consists of a three-state output buffer. the three-state buffer can be congured in one of three ways: always enabled, al- ways disabled, or controlled by a product term. if prod- uct term control is chosen, one of two product terms may be used to provide the control. the two product terms that are available are common to all i/o cells in a pal block. table 1. logic allocation macrocell available clusters output buried m 0 c 0 , c 1 , c 2 m 1 c 0 , c 1 , c 2 , c 3 m 2 c 1 , c 2 , c 3 , c 4 m 3 c 2 , c 3 , c 4 , c 5 m 4 c 3 , c 4 , c 5 , c 6 m 5 c 4 , c 5 , c 6 , c 7 m 6 c 5 , c 6 , c 7 , c 8 m 7 c 6 , c 7 , c 8 , c 9 m 8 c 7 , c 8 , c 9 , c 10 m 9 c 8 , c 9 , c 10 , c 11 m 10 c 9 , c 10 , c 11 , c 12 m 11 c 10 , c 11 , c 12 , c 13 m 12 c 11 , c 12 , c 13 , c 14 m 13 c 12 , c 13 , c 14 , c 15 m 14 c 13 , c 14 , c 15 m 15 c 14 , c 15
8 mach211sp-7/10/12/15/20 these choices make it possible to use the macrocell as an output, an input, a bidirectional pin, or a three-state output for use in driving a bus. power-down mode the mach211sp features a programmable low-power mode in which individual signal paths can be pro- grammed as low power. these low-power speed paths will be slightly slower than the non-low-power paths. this feature allows speed critical paths to run at maxi- mum frequency while the rest of the paths operate in the low-power mode, resulting in power savings of up to 75%. if all signals in a pal block are low-power, then total power is reduced further. in-system programming programming is the process where mach devices are loaded with a pattern de?ed in a jedec ?e obtained from machxl software or third-party software. pro- gramming is accomplished through four jtag pins: test mode select (tms), test clock (tck), test data in (tdi), and test data out (tdo). the mach211sp can be employed in any jtag (ieee 1149.1) compli- ant chain. while the mach211sp is fully jtag com- patible, it supports the bypass instruction, not the extest and sample/preload instructions. the mach211sp can be programmed across the commer- cial temperature range. programming the mach de- vice after it has been placed on a circuit board is easily accomplished. programming is initiated by placing the device into programming mode, using the machpro programming software provided by amd. the device is bulk erased and the jedec ?e is then loaded. after the data is transferred into the device, the program instruction is loaded. further programming details can be found in application note, ?dvanced in-circuit programming guidelines. on-board programming options since the machpro software performs these steps automatically, the following programming options are published for reference. the con?uration ?e, which is also known as the chain ?e, de?es the mach device jtag chain. the ?e con- tains the information concerning which jedec ?e is to be placed into which device, the state which the out- puts should be placed, and whether the security fuses should be programmed. the con?uration ?e is dis- cussed in detail in the machpro software manual. the mach211sp devices tristate the outputs during programming. they have one security bit which inhibits program and verify. this allows the user to protect pro- prietary patterns and designs. program veri?ation of a mach device involves read- ing back the programmed pattern and comparing it with the original jedec ?e. the amd method of program veri?ation performed on the mach devices permits the veri?ation of one device at a time. accidental programming or erasure protection it is virtually impossible to program or erase a mach device inadvertently. the following conditions must be met before programming actually takes place: n the device must be in the password-protected program mode n the programming or bulk erase instruction must be in the instruction register if the above conditions are not met, the programming circuitry cannot be activated. to ensure that the amd ten year device data retention guarantee applies, 100 program/erase cycle limit should not be exceeded. bus-friendly inputs and i/os the mach211sp inputs and i/os include two inverters in series which loop back to the input. this double inversion reinforces the state of the input and pulls the voltage away from the input threshold voltage. for an illustration of this con?uration, please turn to the input/output equivalent schematics section. pci compliance the mach211sp-7/10 is fully compliant with the pci local bus speci?ation published by the pci special interest group. the mach211sp-7/10s predictable timing ensures compliance with the pci ac speci?a- tions independent of the design. on the other hand, in cpld and fpga architectures without predictable tim- ing, pci compliance is dependent upon routing and product term distribution.
mach211sp-7/10/12/15/20 9 0 4 8 12 16 20 24 28 40 32 43 36 0 4 8 12 16 20 24 28 40 32 43 36 i/o cell i/o i/o i/o i/o i/o i/o i/o i/o switch matrix output enable output enable asynchronous reset asynchronous preset 16 i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell output macro cell 8 buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell buried macro cell 47 51 47 51 clk 2 0 logic allocator 63 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 m 12 m 13 m 14 m 15 20405b-4 figure 1. mach211sp pal block
10 mach211sp-7/10 (coml) absolute maximum ratings storage temperature . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?5 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . .?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 70 c) . . . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air. . . . . . . . . . . . . . . .0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . +4.75 v to +5.25 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise speci?d notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is measured in low-power mode with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled and reset. 5. this parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (notes 3, 5) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
mach211sp-7/10 (coml) 11 capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description -7 -10 unit min max min max t pd input, i/o, or feedback to combinatorial output (note 3) 7.5 10 ns t s setup time from input, i/o, or feedback to clock (note 3) d-type 5.5 6.5 ns t-type 6.5 7.5 ns t h register data hold time 0 0 ns t co clock to output (note 3) 4.5 6 ns t wl clock width low 3 5 ns t wh high 3 5 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 100 80 mhz t-type 91 74 mhz internal feedback (f cnt ) d-type 133 100 mhz t-type 125 91 mhz no feedback 1/(t wl + t wh ) 166.7 100 mhz t sl setup time from input, i/o, or feedback to gate 5.5 6.5 ns t hl latch data hold time 0 0 ns t go gate to output 7 7 ns t gwl gate width low 3 5 ns t pdl input, i/o, or feedback to output through transparent input or output latch 9.5 12 ns t sir input register setup time 2 2 ns t hir input register hold time 2 2 ns t ico input register clock to combinatorial output 11 13 ns t ics input register clock to output register setup d-type 9 10 ns t-type 10 11 ns t wicl input register clock width low 3 5 ns t wich high 3 5 ns f maxir maximum input register frequency 166.7 100 mhz t sil input latch setup time 2 2 ns t hil input latch hold time 2 2 ns t igo input latch gate to combinatorial output 12 14 ns t igol input latch gate to output through transparent output latch 14 16 ns t sll setup time from input, i/o, or feedback through transparent input latch to output latch gate 7.5 8.5 ns
12 mach211sp-7/10 (coml) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d where frequency may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. t igs input latch gate to output latch setup 10 11 ns t wigl input latch gate width low 3 5 ns t pdll input, i/o, or feedback to output through transparent input and output latches 12.5 14 ns t ar asynchronous reset to registered or latched output 9.5 15 ns t arw asynchronous reset width (note 1) 5 10 ns t arr asynchronous reset recovery time (note 1) 5 10 ns t ap asynchronous preset to registered or latched output 9.5 15 ns t apw asynchronous preset width (note 1) 5 10 ns t apr asynchronous preset recovery time (note 1) 5 10 ns t ea input, i/o, or feedback to output enable (note 1) 9.5 12 ns t er input, i/o, or feedback to output disable (note 1) 9.5 12 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 ns t lps t s increase for powered-down macrocell (note 3) 10 10 ns t lpco t co increase for powered-down macrocell (note 3) 0 0 ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 ns switching characteristics over commercial operating ranges (note 2) (continued) parameter symbol parameter description -7 -10 unit min max min max
MACH211SP-12/15/20 (coml) 13 absolute maximum ratings storage temperature . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?5 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . .?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = 0 c to 70 c) . . . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air. . . . . . . . . . . . . . . .0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . +4.75 v to +5.25 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over commercial operating ranges unless otherwise speci?d notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is measured in low-power mode with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled and reset. 5. this parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (notes 3, 5) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
14 MACH211SP-12/15/20 (coml) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf switching characteristics over commercial operating ranges (note 2) parameter symbol parameter description -12 -15 -20 unit min max min max min max t pd input, i/o, or feedback to combinatorial output (note 3) 12 15 20 ns t s setup time from input, i/o, or feedback to clock d-type 7 10 13 ns t-type 8 11 14 ns t h register data hold time 0 0 0 ns t co clock to output (note 3) 8 10 12 ns t wl clock width low 6 6 8 ns t wh high 6 6 8 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 66.7 50 40 mhz t-type 62.5 47.6 38.5 mhz internal feedback (f cnt ) d-type 83.3 66.6 50 mhz t-type 76.9 62.5 47.6 mhz no feedback 1/(t wl + t wh ) 83.3 83.3 62.5 mhz t sl setup time from input, i/o, or feedback to gate 7 10 13 ns t hl latch data hold time 0 0 0 ns t go gate to output 10 11 12 ns t gwl gate width low 6 6 8 ns t pdl input, i/o, or feedback to output through transparent input or output latch 14 17 22 ns t sir input register setup time 2 2 2 ns t hir input register hold time 2 2.5 3 ns t ico input register clock to combinatorial output 15 18 23 ns t ics input register clock to output register setup d-type 12 15 20 ns t-type 13 16 21 ns t wicl input register clock width low 6 6 8 ns t wich high 6 6 8 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 83.3 83.3 62.5 mhz t sil input latch setup time 2 2 2 ns t hil input latch hold time 2 2.5 3 ns
MACH211SP-12/15/20 (coml) 15 notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d where frequency may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. t igo input latch gate to combinatorial output 17 20 25 ns t igol input latch gate to output through transparent output latch 19 22 27 ns t sll setup time from input, i/o, or feedback through transparent input latch to output latch gate 91215ns t igs input latch gate to output latch setup 13 16 21 ns t wigl input latch gate width low 6 6 8 ns t pdll input, i/o, or feedback to output through transparent input and output latches 16 19 24 ns t ar asynchronous reset to registered or latched output 16 20 25 ns t arw asynchronous reset width (note 1) 12 15 20 ns t arr asynchronous reset recovery time (note 1) 8 10 15 ns t ap asynchronous preset to registered or latched output 16 20 25 ns t apw asynchronous preset width (note 1) 12 15 20 ns t apr asynchronous preset recovery time (note 1) 8 10 15 ns t ea input, i/o, or feedback to output enable (note 1) 15 15 15 ns t er input, i/o, or feedback to output disable (note 1) 15 15 15 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 10 ns t lps t s increase for powered-down macrocell (note 3) 10 10 10 ns t lpco t co increase for powered-down macrocell (note 3) 000ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 10 ns switching characteristics over commercial operating ranges (note 2) (continued) parameter symbol parameter description -12 -15 -20 unit min max min max min max
16 mach211sp-10/12 (ind) absolute maximum ratings storage temperature . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?5 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . .?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = ?0 c to +85 c). . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges industrial (i) devices temperature (t a ) operating in free air. . . . . . . . . . . . . .?0 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over industrial operating ranges unless otherwise speci?d notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is measured in low-power mode with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled and reset. 5. this parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (notes 3, 5) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
mach211sp-10/12 (ind) 17 capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf switching characteristics over industrial operating ranges (note 2) parameter symbol parameter description -10 -12 unit min max min max t pd input, i/o, or feedback to combinatorial output (note 3) 10 12 ns t s setup time from input, i/o, or feedback to clock d-type 6.5 8 ns t-type 7.5 9 ns t h register data hold time 0 0 ns t co clock to output (note 3) 6 7.5 ns t wl clock width low 5 6 ns t wh high 5 6 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 80 64 mhz t-type 74 59 mhz internal feedback (f cnt ) d-type 100 80 mhz t-type 91 72.5 mhz no feedback 1/(t wl + t wh ) 100 80 mhz t sl setup time from input, i/o, or feedback to gate 6.5 8 ns t hl latch data hold time 0 0 ns t go gate to output 8 8.5 ns t gwl gate width low 5 6 ns t pdl input, i/o, or feedback to output through transparent input or output latch 12 14.5 ns t sir input register setup time 2 2.5 ns t hir input register hold time 2 3 ns t ico input register clock to combinatorial output 13 16 ns t ics input register clock to output register setup d-type 10 12 ns t-type 11 13 ns t wicl input register clock width low 5 6 ns t wich high 5 6 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 100 80 mhz t sil input latch setup time 2 2.5 ns t hil input latch hold time 2 3 ns t igo input latch gate to combinatorial output 14 17 ns t igol input latch gate to output through transparent output latch 16 19.5 ns
18 mach211sp-10/12 (ind) notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. t sll setup time from input, i/o, or feedback through transparent input latch to output latch gate 8.5 10.5 ns t igs input latch gate to output latch setup 11 13.5 ns t wigl input latch gate width low 5 6 ns t pdll input, i/o, or feedback to output through transparent input and output latches 14 17 ns t ar asynchronous reset to registered or latched output 15 19.5 ns t arw asynchronous reset width (note 1) 10 12 ns t arr asynchronous reset recovery time (note 1) 10 10 ns t ap asynchronous preset to registered or latched output 15 18 ns t apw asynchronous preset width (note 1) 10 12 ns t apr asynchronous preset recovery time (note 1) 10 10 ns t ea input, i/o, or feedback to output enable (note 1) 15 15 ns t er input, i/o, or feedback to output disable (note 1) 15 15 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 ns t lps t s increase for powered-down macrocell (note 3) 10 10 ns t lpco t co increase for powered-down macrocell (note 3) 0 0 ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 ns switching characteristics over industrial operating ranges (note 2) (continued) parameter symbol parameter description -10 -12 unit min max min max
mach211sp-14/18/24 (ind) 19 absolute maximum ratings storage temperature . . . . . . . . . . . . ?5 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?5 c to +125 c supply voltage with respect to ground . . . . . . . . . . . . . . . ?.5 v to +7.0 v dc input voltage . . . . . . . . . . . .?.5 v to v cc + 0.5 v dc output or i/o pin voltage . . . . . . . . . . . . . .?.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2001 v latchup current (t a = ?0 c to 85 c) . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device reliability. programming conditions may differ. operating ranges industrial (i) devices ambient temperature (t a ) operating in free air. . . . . . . . . . . . . .?0 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?e those limits between which the functionality of the device is guaranteed. dc characteristics over industrial operating ranges unless otherwise speci?d notes: 1. these are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 4. this parameter is measured in low-power mode with a 16-bit up/down counter pattern. this pattern is programmed in each pal block and is capable of being loaded, enabled and reset. 5. this parameter is not 100% tested, but is evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v v ol output low voltage i ol = 16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 1) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 1) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 2) 10 m a i il input low leakage current v in = 0 v, v cc = max (note 2) ?0 m a i ozh off-state output leakage current high v out = 5.25 v, v cc = max v in = v ih or v il (note 2) 10 m a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ?0 m a i sc output short-circuit current v out = 0.5 v, v cc = max (notes 3, 5) ?0 ?60 ma i cc supply current (static) v cc = 5 v, t a = 25 c, f = 0 mhz (note 4) 40 ma supply current (active) v cc = 5 v, t a = 25 c, f = 1 mhz (note 4) 45 ma
20 mach211sp-14/18/24 (ind) capacitance (note 1) parameter symbol parameter description test conditions typ unit c in input capacitance v in = 2.0 v v cc = 5.0 v, t a = 25 c f = 1 mhz 6pf c out output capacitance v out = 2.0 v 8 pf switching characteristics over industrial operating ranges (note 2) parameter symbol parameter description -14 -18 -24 unit min max min max min max t pd input, i/o, or feedback to combinatorial output (note 3) 14.5 18 24 ns t s setup time from input, i/o, or feedback to clock d-type 8.5 12 16 ns t-type 10 13.5 17 ns t h register data hold time 0 0 0 ns t co clock to output (note 3) 10 12 14.5 ns t wl clock width low 7.5 7.5 10 ns t wh high 7.5 7.5 10 ns f max maximum frequency (note 1) external feedback 1/(t s + t co ) d-type 53 40 32 mhz t-type 50 38 30.5 mhz internal feedback (f cnt ) d-type 61.5 53 38 mhz t-type 57 44 34.5 mhz no feedback 1/(t wl + t wh ) 66.5 66.5 50 mhz t sl setup time from input, i/o, or feedback to gate 8.5 12 16 ns t hl latch data hold time 0 0 0 ns t go gate to output 12 13.5 14.5 ns t gwl gate width low 7.5 7.5 10 ns t pdl input, i/o, or feedback to output through transparent input or output latch 17 20.5 26.5 ns t sir input register setup time 2.5 2.5 2.5 ns t hir input register hold time 3 3.5 4 ns t ico input register clock to combinatorial output 18 22 28 ns t ics input register clock to output register setup d-type 14.5 18 24 ns t-type 16 19.5 25.5 ns t wicl input register clock width low 7.5 7.5 10 ns t wich high 7.5 7.5 10 ns f maxir maximum input register frequency 1/(t wicl + t wich ) 66.5 66.5 50 mhz t sil input latch setup time 2.5 2.5 2.5 ns t hil input latch hold time 3 3.5 4 ns t igo input latch gate to combinatorial output 20.5 24 30 ns
mach211sp-14/18/24 (ind) 21 notes: 1. these parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modi?d where capacitance may be affected. 2. see switching test circuit for test conditions. 3. if a signal is powered-down, this parameter must be added to its respective high-speed parameter. t igol input latch gate to output through transparent output latch 23 26.5 32.5 ns t sll setup time from input, i/o, or feedback through transparent input latch to output latch gate 11 14.5 18 ns t igs input latch gate to output latch setup 16 19.5 25.5 ns t wigl input latch gate width low 7.5 7.5 10 ns t pdll input, i/o, or feedback to output through transparent input and output latches 19.5 23 29 ns t ar asynchronous reset to registered or latched output 19.5 24 30 ns t arw asynchronous reset width (note 1) 14.5 18 24 ns t arr asynchronous reset recovery time (note 1) 10 12 18 ns t ap asynchronous preset to registered or latched output 19.5 24 30 ns t apw asynchronous preset width (note 1) 14.5 18 24 ns t apr asynchronous preset recovery time (note 1) 10 12 18 ns t ea input, i/o, or feedback to output enable (note 1) 14.5 18 24 ns t er input, i/o, or feedback to output disable (note 1) 14.5 18 24 ns t lp t pd increase for powered-down macrocell (note 3) 10 10 10 ns t lps t s increase for powered-down macrocell (note 3) 10 10 10 ns t lpco t co increase for powered-down macrocell (note 3) 000ns t lpea t ea increase for powered-down macrocell (note 3) 10 10 10 ns switching characteristics over industrial operating ranges (note 2) (continued) parameter symbol parameter description -14 -18 -24 unit min max min max min max
22 mach211sp-7/10/12/15/20 typical i cc characteristics v cc = 5 v, t a = 25 c the selected ?ypical pattern is a 16-bit up/down counter. this pattern is programmed in each pal block and is capable of being loaded, enabled, and reset. maximum frequency shown uses internal feedback and a d-type register. 100 150 50 0 0 10203040 5060708090 200 i cc (ma) frequency (mhz) high speed low power 20405b-5
mach211sp-7/10/12/15/20 23 typical thermal characteristics measured at 25 c ambient. these parameters are not tested. plastic q jc considerations the data listed for plastic q jc are for reference only and are not recommended for use in calculating junction temperatures. the heat-?w paths in plastic-encapsulated devices are complex, making the q jc measurement relative to a speci? location on the package surface. tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. furthermore, q jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. therefore, the measurements can only be used in a similar environment. tqfp thermal measurements are taken with components on a six-layer printed circuit board. parameter symbol parameter description typ unit tqfp plcc q jc thermal impedance, junction to case 11.3 4 c/w q ja thermal impedance, junction to ambient 41 30.4 c/w q jma thermal impedance, junction to ambient with air ?w 200 lfpm air 35 18.5 c/w 400 lfpm air 33.7 15.9 c/w 600 lfpm air 32.6 13.5 c/w 800 lfpm air 32 12.8 c/w
24 mach211sp-7/10/12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. 20405b-6 combinatorial output t pd input, i/o, or feedback combinatorial output v t v t 20405b-7 20405b-8 registered output latched output v t input, i/o, or feedback registered output t s t co v t t h v t clock t pdl input, i/o, or feedback latched out gate v t t hl t sl t go v t v t 20405b-9 20405b-10 clock width gate width t wh clock t wl gate t gwl v t 20405b-11 20405b-12 registered input input register to output register setup v t combinatorial output t sir t ico v t t hir v t input register clock registered input v t v t v t t ics output register clock input register clock registered input
mach211sp-7/10/12/15/20 25 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. 20405b-13 latched input combinatorial output gate t hil t sil t igo latched in v t v t v t 20405b-14 latched input and output latched in output latch gate latched out t sll t pdll t igol t igs input latch gate v t v t v t
26 mach211sp-7/10/12/15/20 switching waveforms notes: 1. v t = 1.5 v. 2. input pulse amplitude 0 v to 3.0 v. 3. input rise and fall times 2 ns? ns typical. 20405b-15 20405b-16 input register clock width input latch gate width t wich clock v t t wicl input latch gate t wigl v t 20405b-17 20405b-18 asynchronous reset asynchronous preset v t v t t arw v t t ar input, i/o, or feedback registered output or latched output clock or input latch gate t arr input, i/o, or feedback v t v t t apw v t t ap t apr registered output or latched output clock or input latch gate 20405b-19 output disable/enable v t v t outputs t er t ea v oh ?0.5 v v ol + 0.5 v input, i/o, or feedback
mach211sp-7/10/12/15/20 27 key to switching waveforms switching test circuit * switching several outputs simultaneously should be avoided for accurate measurement. speci?ation s 1 c l commercial measured output value r 1 r 2 t pd , t co closed 35 pf 300 w 390 w 1.5 v t ea z ? h: open z ? l: closed t er h ? z: open l ? z: closed 5 pf h ? z: v oh ?0.5 v l ? z: v ol + 0.5 v must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010-pal 20405b-20 c l output r 1 r 2 s 1 test point 5 v
28 mach211sp-7/10/12/15/20 f max parameters the parameter f max is the maximum clock rate at which the device is guaranteed to operate. because the ?xi- bility inherent in programmable logic devices offers a choice of clocked ?p-?p designs, f max is speci?d for three types of synchronous designs. the ?st type of design is a state machine with feed- back signals sent off-chip. this external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. the slowest path de?ing the period is the sum of the clock-to-output time and the input setup time for the external signals (t s + t co ). the reciprocal, f max , is the maximum frequency with exter- nal feedback or in conjunction with an equivalent speed device. this f max is designated ? max external. the second type of design is a single-chip state ma- chine with internal feedback only. in this case, ?p-?p inputs are de?ed by the device inputs and ?p-?p out- puts. under these conditions, the period is limited by the internal delay from the ?p-?p outputs through the internal feedback and logic to the ?p-?p inputs. this f max is designated ? max internal? a simple internal counter is a good example of this type of design; there- fore, this parameter is sometimes called ? cnt. the third type of design is a simple data path applica- tion. in this case, input data is presented to the ?p-?p and clocked through; no feedback is employed. under these conditions, the period is limited by the sum of the data setup time and the data hold time (t s + t h ). how- ever, a lower limit for the period of each f max type is the minimum clock period (t wh + t wl ). usually, this mini- mum clock period determines the period for the third f max , designated ? max no feedback. for devices with input registers, one additional f max pa- rameter is speci?d: f maxir . because this involves no feedback, it is calculated the same way as f max no feedback. the minimum period will be limited either by the sum of the setup and hold times (t sir + t hir ) or the sum of the clock widths (t wicl + t wich ). the clock widths are normally the limiting parameters, so that f maxir is speci?d as 1/(t wicl + t wich ). note that if both input and output registers are use in the same path, the overall frequency will be limited by t ics . all frequencies except f max internal are calculated from other measured ac parameters. f max internal is mea- sured directly. t sir clk logic register clk logic register t s clk logic register f max external; 1/(t s + t co )f max internal (f cnt ) f max no feedback; 1/(t s + t h ) or 1/(t wh + t wl )f maxir ; 1/(t sir + t hir ) or 1/(t wicl + t wich ) t s t co t s clk logic register (second chip) t hir 20405b-21
mach211sp-7/10/12/15/20 29 endurance characteristics the mach families are manufactured using amd? ad- vanced electrically erasable process. this technology uses an ee cell to replace the fuse link used in bipolar parts. as a result, the device can be erased and repro- grammed, a feature which allows 100% testing at the factory. endurance characteristics parameter symbol parameter description min units test conditions t dr min pattern data retention time 10 years max storage temperature 20 years max operating temperature n max reprogramming cycles 100 cycles normal programming conditions
30 mach211sp-7/10/12/15/20 input/output equivalent schematics v cc esd protection 1 k w input v cc 100 k w preload circuitry feedback input i/o v cc v cc 100 k w 1 k w 20405b-22
mach211sp-7/10/12/15/20 31 power-up reset the mach devices have been designed with the capa- bility to reset during system power-up. following power-up, all ?p-?ps will be reset to low. the output state will depend on the logic polarity. this feature pro- vides extra ?xibility to the designer and is especially valuable in simplifying state machine initialization. a timing diagram and parameter table are shown below. due to the synchronous operation of the power-up reset and the wide range of ways v cc can rise to its steady state, two conditions are required to insure a valid power-up reset. these conditions are: 1. the v cc rise must be monotonic. 2. following reset, the clock input must not be driven from low to high until all applicable input and feedback setup times are met. parameter symbol parameter descriptions max unit t pr power-up reset time 10 m s t s input or feedback setup time see switching characteristics t wl clock width low 20405b-23 power-up reset waveform t pr t wl t s 4 v v cc power registered output clock
32 mach211sp-7/10/12/15/20 development systems (subject to change) for more information on the products listed below, please consult the amd fusionpld catalog. manufacturer software development systems advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 machxl software ver. 3.0 advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 design center/amd software advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 amd-abel software data i/o mach fitters advanced micro devices, inc. p.o. box 3453, ms 1028 sunnyvale, ca 94088-3543 (800) 222-9323 or (408) 732-2400 prodeveloper/amd software prosynthesis/amd software cadence design systems 555 river oaks pkwy san jose, ca 95134 (408) 943-1234 pld designer verilog, leapfrog, rapidsim simulators ver. 9504 data i/o corporation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 332-8246 or (206) 881-6444 abel software synario software mentor graphics corp. 8005 s.w. boeckman rd. wilsonville, or 97070-7777 (800) 547-3000 or (503) 685-7000 pldsynthesis ii quicksim simulator microsim corp. 20 fairbanks irvine, ca 92718 (714) 770-3022 design center software minc incorporated 6755 earl drive, suite 200 colorado springs, co 80918 (800) 755-fpga or (719) 590-1155 pldesigner-xl software susie-cad 10000 nevada highway, suite 201 boulder city, nv 89005 (702) 293-2271 susie simulator synopsys logic modeling 19500 nw gibbs dr. p.o. box 310 beaverton, or 97075 (503) 690-6900 smartmodel library teradyne eda 321 harrison ave. boston, ma 02118 (800) 777-2432 or (617) 422-2793 multisim interactive simulator lasar
mach211sp-7/10/12/15/20 33 development systems (subject to change) (continued) advanced micro devices is not responsible for any information relating to the products of third parties. the inclusion of such information is not a representation nor an endorsement by amd of these products. manufacturer software development systems viewlogic systems, inc. 293 boston post road west marlboro, ma 01752 (800) 442-4660 or (508) 480-0881 viewpld or propld (requires prosim simulator mach fitter) viewsim simulator manufacturer test generation system acugen software, inc. 427-3 amherst st., suite 391 nashua, nh 03063 (603) 891-1995 atgen test generation software int gmbh busenstrasse 6 d-8033 martinsried, munich, germany (87) 857-6667 pldcheck 90
34 mach211sp-7/10/12/15/20 approved programmers (subject to change) for more information on the products listed below, please consult the amd fusionpld catalog. manufacturer programmer configuration advin systems, inc. 1050-l east duane ave. sunnyvale, ca 94086 (408) 243-7000 pilot u84 bp microsystems 100 n. post oak rd. houston, tx 77055-7237 (800) 225-2102 or (713) 688-4600 bp1148 bp1200 bp2100 data i/o corporation 10525 willows road n.e. p.o. box 97046 redmond, wa 98073-9746 (800) 332-8246 or (206) 881-6444 unisite model 2900 model 3900 autosite hi/lo 4f, no. 2, sec. 5, ming shoh e. rd. taipei, taiwan all-07 flex-700 logical devices inc./digelec 692 s. military trail deer?ld beach, fl 33442 (800) 331-7766 or (305) 428-6868 allpro-88 sms north america, inc. 16522 ne 135th place redmond, wa 98052 (800) 722-4122 or sms lm grund 15 d-7988 vangen im allgau, germany 07522-5018 sprint expert multisite stag microsystems inc. 1600 wyatt dr. suite 3 santa clara, ca 95054 (408) 988-1118 or stag house martin?ld, welwyn garden city herfordshire uk al7 1jt 707-332148 stag quazar stag eclipse system general 510 s. park victoria dr. milpitas, ca 95035 (408) 263-6667 or 3f, no. 1, alley 8, lane 45 bao shing rd., shin diau taipei, taiwan 2-917-3005 turpro-1 fx tx
mach211sp-7/10/12/15/20 35 approved on-board programmers programmer socket adapters (subject to change) manufacturer programmer configuration corelis, inc. 12607 hidden creek way, suite h cerritos, california 70703 (310) 926-6727 jtag prog advanced micro devices p.o. box 3453, ms-1028 sunnyvale, ca 94088-3453 (800) 222-9323 machpro manufacturer part number california integration technologies 656 main street placerville, ca 95667 (916) 626-6168 contact manufacturer edi corporation p.o. box 366 patterson, ca 95363 (209) 892-3270 contact manufacturer emulation technology 2344 walsh ave., bldg. f santa clara, ca 95051 (408) 982-0660 contact manufacturer logical systems corp. p.o. box 6184 syracuse, ny 13217-6184 (315) 478-0722 contact manufacturer procon technologies, inc. 1333 lawrence expwy, suite 207 santa clara, ca 95051 (408) 246-4456 contact manufacturer
36 mach211sp-7/10/12/15/20 physical dimensions* pl 044 44-pin plastic leaded chip carrier (measured in inches) * for reference only. bsc is an ansi standard for basic space centering. top view seating plane .685 .695 .650 .656 pin 1 i.d. .685 .695 .650 .656 .026 .032 .050 ref .042 .056 .062 .083 .013 .021 .590 .630 .500 ref .009 .015 .165 .180 .090 .120 16-038-sq pl 044 da78 6-28-94 ae side view
mach211sp-7/10/12/15/20 37 physical dimensions pqt044 44-pin thin quad flat pack (measured in millimeters) trademarks copyright ? 1996 advanced micro devices, inc. all rights reserved. amd, the amd logo, mach, and pal are registered trademarks of advanced micro devices, inc. bus-friendly is a trademark of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies. 1.00 ref. 1.20 max 11 ?13 11 ?13 0.80 bsc 44 1 0.95 1.05 11.80 12.20 9.80 10.20 11.80 12.20 9.80 10.20 0.30 0.45 16-038-pqt-2 pqt 44 7-11-95 ae

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